For instance, if there are both main.c and main.s files in the directory, make uses the. Make uses the order of appearance in the suffixes list to determine which dependency file and suffix rule to use. o file from a dependency file that has the same base name and a. It checks for an appropriate implicit rule to apply. Table 4-6 Makefile for Compiling C Sources Using Suffix Rules # Makefile for a program from two C sourcesĪ complete list of suffix rules appears in Table 4-8.Īs make processes the dependencies main.o and data.o, it finds no target entries for them. c.o rule to compile the individual object files. This next version of the makefile eliminates them, relying on the.
c.o suffix rule, their target entries are redundant make performs the same compilation whether they appear in the makefile or not. c files are now functionally equivalent to the. Since the command lines for compiling main.o and data.o from their. Using Implicit Rules to Simplify a Makefile: Suffix Rules Table 4-5 Makefile for Compiling C Sources Using Predefined Macros # Makefile for compiling two C sources Options for the link editor, ld none by default. Options for the cc command none by default. (You can redefine the value to be the path name of an alternate C compiler.) CFLAGS The basic cc command line to link object files, such as COMPILE.c, but without the -c option and with a reference to the LDFLAGS macro: LINK.c=$(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) CC The complete list of all predefined macros is shown in Table 4-9. It is also good practice to note the desired default values for them in the makefile. It is good practice to use these macros for consistency and portability. Macro names that end in the string FLAGS pass options to a related compiler-command macro. c suffix is a mnemonic device to indicate that the command line applies to. The root of the macro name, COMPILE, is a convention used to indicate that the macro stands for a compilation command line (to generate an object, or. The cc command line composed of the values of CC, CFLAGS, and CPPFLAGS, as follows, along with the -c option. ] They are generally useful for compiling C programs. Not all of the predefined macros shown here are available [Predefined macros are used more extensively than in earlier The predefined macros in the following makefile are listed below. Predefined macros are also used extensively within make's implicit rules.
Macros also provide access to the CFLAGS macro (and other FLAGS macros) for supplying compiler options from the command line. Using predefined macros eliminates the need to edit makefiles when the underlying compilation environment changes. The next example performs exactly the same function, but demonstrates the use of make's predefined macros for the indicated compilation commands. In this example, make produces the object files main.o and data.o, and the executable file functions: $ makeĬc -O -c data.c Using make's Predefined Macros Table 4-4 Simple Makefile for Compiling C Sources: Everything Explicit # Simple makefile for compiling a program from The following makefile is not elegant, but it does the job. This method requires more disk space, but subsequent (repetitive) recompilations need to be performed only on those object files for which the sources have changed, which saves time. o) file, and then by linking the object files to form an executable ( a.out) file. Many include library routines, either from one of the standard system libraries or from a user-supplied library.Īlthough it might be easier to recompile and link a single-source program using a single cc command, it is usually more convenient to compile programs with multiple sources in stages-first, by compiling each source file into a separate object (. Most C programs, however, are compiled from several source files.
SIMPLE C MAKEFILE EXAMPLE HOW TO
In previous examples you have seen how to compile a simple C program from a single source file, using both explicit target entries and implicit rules.
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